Sloped bonding structure for semiconductor package

ABSTRACT

A bonding structure includes a substrate having a top surface and including at least one bonding pad. Each bonding pad is disposed adjacent to the top surface of the substrate and has a sloped surface. A semiconductor element includes at least one pillar. Each pillar is bonded to a portion of the sloped surface of a corresponding bonding pad, and a gap is formed between a sidewall of the pillar and the sloped surface of the corresponding bonding pad.

BACKGROUND

1. Technical Field

The present disclosure relates to a semiconductor package and method ofmanufacturing the same, and, more particularly, to a bonding structurefor a semiconductor package and method of manufacturing the same.

2. Description of the Related Art

In a known semiconductor flip-chip bonding process, a nickel layer isplated on a metal pillar of an upper chip to serve as a barrier layer,and then a solder is formed on the nickel layer. Next, the upper chip isplaced on a lower chip or a substrate, where the solder on the metalpillar will contact a surface finish layer on a bonding pad of the lowerchip or the substrate. Then, a reflow process is performed to melt thesolder and to bond the metal pillar to the bonding pad, to form aflip-chip bonding structure.

In the known process, a large amount of solder is used in order toprovide effective bonding between the metal pillar and the bonding pad.Since the outer diameter of the solder cannot be effectively decreased,a pitch between the metal pillars cannot be effectively reduced. Inaddition, to make the solder reach a molten state, the solder is heatedto above 300° C. However, in such a high-temperature environment, theupper chip, the lower chip or the substrate is prone to warping, and themetal pillar is easily oxidized. To avoid oxidation of the metal pillar,another known technique is to perform high-temperature bonding in avacuum environment. However, such a technique will increase themanufacturing cost, and cannot solve the warpage problem.

Moreover, to make the reflow process of the solder be carried out at alower temperature, a solder is typically used with a reflux agent or anorganic compound. Removal of such reflux agent or organic compoundafterwards typically will raise environmental issues. Addressing theseissues will incur additional cost.

Therefore, it is desirable to provide a semiconductor bonding structureand process that can solve the above problems.

SUMMARY

One aspect of the present disclosure relates to a bonding structureuseful for a semiconductor package. In an embodiment, the bondingstructure comprises a substrate and a semiconductor element. Thesubstrate has a top surface and includes at least one bonding padwherein each bonding pad is disposed adjacent to the top surface of thesubstrate and has a sloped surface. The semiconductor element includesat least one pillar, wherein each pillar is bonded to a portion of thesloped surface of a corresponding one of the at least one bonding pad,and a gap is formed between a sidewall of the pillar and the slopedsurface of the corresponding bonding pad.

Another aspect of the present disclosure relates to a bonding structureuseful for a semiconductor package. In an embodiment, the bondingstructure comprises a substrate and a semiconductor element. Thesubstrate has a top surface and includes at least one bonding pad,wherein each bonding pad is disposed adjacent to the top surface of thesubstrate and has a sloped surface with a first slope L1. Thesemiconductor element includes at least one pillar, wherein each pillaris bonded to a portion of the sloped surface of a corresponding one ofthe at least one bonding pad and has a sidewall with a second slope L2.The absolute value of the first slope L1 is less than the absolute valueof the second slope L2.

Another aspect of the present disclosure relates to a method ofmanufacturing a bonding structure useful in a semiconductor package. Inan embodiment, the method comprises: providing a substrate, wherein thesubstrate includes a top surface and at least one bonding pad disposedadjacent to the top surface of the substrate, at least one bonding padhaving a sloped surface with a first slope L1; providing a semiconductorelement, wherein the semiconductor element includes at least one pillar,and at least one pillar has a sidewall with a second slope L2, whereinthe absolute value of the first slope L1 is smaller than the absolutevalue of the second slope L2; and bonding at least one pillar to aportion of the sloped surface of corresponding ones of the at least onebonding pad.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a cross-sectional view of a semiconductor packageaccording to an embodiment of the present disclosure.

FIG. 1A illustrates an enlarged view of a bonding structure in thesemiconductor package illustrated in FIG. 1 according to one embodimentof the present disclosure.

FIG. 1B illustrates an enlarged view of a bonding structure in thesemiconductor package illustrated in FIG. 1 according to anotherembodiment of the present disclosure.

FIG. 2 illustrates a cross-sectional view of a semiconductor packageaccording to another embodiment of the present disclosure.

FIG. 2A illustrates an enlarged view of a bonding structure in thesemiconductor package illustrated in FIG. 2 according to one embodimentof the present disclosure.

FIG. 2B illustrates an enlarged view of a bonding structure in thesemiconductor package illustrated in FIG. 2 according to anotherembodiment of the present disclosure.

FIG. 3 illustrates a cross-sectional view of a semiconductor packageaccording to another embodiment of the present disclosure.

FIG. 4A, FIG. 4B, FIG. 4C, FIG. 4D, FIG. 4E, FIG. 4F, FIG. 4G, FIG. 4H,FIG. 4I, FIG. 4J, and FIG. 4K illustrate a method for manufacturing asemiconductor package according to an embodiment of the presentdisclosure.

FIG. 5A and FIG. 5B illustrate a method for manufacturing asemiconductor package according to another embodiment of the presentdisclosure.

DETAILED DESCRIPTION

Spatial descriptions, such as “above,” “below,” “up,” “left,” “right,”“down,” “top,” “bottom,” “vertical,” “horizontal,” “side,” “higher,”“lower,” “upper,” “over,” “under,” and so forth, are specified withrespect to a certain element or certain plane of an element, asdescribed in the specification and shown in the figures. Furthermore, itshould be understood that the spatial descriptions used herein are forpurposes of illustration only, and that practical implementations of thestructures described herein can be spatially arranged in any orientationor manner, provided that the merits of embodiments of this disclosureare not deviated by such arrangement.

FIG. 1 illustrates a cross-sectional view of a semiconductor package 100according to an embodiment of the present disclosure. The semiconductorpackage 100 comprises a substrate 102, a semiconductor element 104, anunderfill 110 and a plurality of connecting elements 112 for externalconnection.

The substrate 102 can be made of, for example, ceramic, glass-reinforcedepoxy (e.g., FR4), polyimide, silicon, or Bismaleimide/Triazine (BT)resin. The substrate 102 has a top surface 102 a, a bottom surface 102b, a side surface 102 c, a lower circuit layer 114, a lower insulationlayer 116, at least one conductive via 118, at least one bonding pad 108and at least one cavity 120. The top surface 102 a is opposite to thebottom surface 102 b. A side surface 102 c extends between the topsurface 102 a and the bottom surface 102 b.

The lower circuit layer 114 is disposed adjacent to the bottom surface102 b of the substrate 102. The lower insulation layer 116 substantiallycovers the lower circuit layer 114 and the bottom surface 102 b of thesubstrate 102, and has a plurality of openings 1161 to expose at least aportion of the lower circuit layer 114 so that the lower circuit layer114 can electrically connect to the external environment through theconnecting elements 112 disposed in the openings 1161. The lower circuitlayer 114 may comprise, for example, copper or other metal, or a metalalloy. In one embodiment, the lower insulation layer 116 is a soldermask, the material of which is, for example, a polyimide (PI).

The conductive vias 118 extend from the top surface 102 a of thesubstrate 102 to the bottom surface 102 b of the substrate 102 so as toprovide an electrical connection between the lower circuit layer 114 andthe bonding pads 108. In addition, in this embodiment, the substrate 102defines the cavities 120 for the bonding pads 108 to be disposed in. Abonding pad 108 may be electrically connected to and aligned with arespective one of the conductive vias 118. In this embodiment, one endof a conductive via 118 connects to the lower circuit layer 114, and theother end of the conductive via 118 connects to the bottom portion of abonding pad 108. The material of the conductive via 118 may comprisecopper or other metal, or a metal alloy. The bonding pads 108 maycomprise, for example, one of, or a combination of, copper, gold,indium, tin, silver, palladium, osmium, iridium, ruthenium, titanium,magnesium, aluminum, cobalt, nickel, or zinc.

The semiconductor element 104 may be a chip, a package, or aninterposer. The semiconductor element 104 has a first surface 104 a, asecond surface 104 b, a side surface 104 c, at least one pad 122, aninsulation layer 124, at least one under bump metallization (UBM) 126,and at least one pillar 106. The first surface 104 a is opposite to thesecond surface 104 b. The side surface 104 c extends between the firstsurface 104 a and the second surface 104 b. The pads 122 are disposed onthe first surface 104 a of the semiconductor element 104. The pads 122may comprise, for example, one of, or a combination of, copper, gold,indium, tin, silver, palladium, osmium, iridium, ruthenium, titanium,magnesium, aluminum, cobalt, nickel, or zinc.

The insulation layer 124 covers a portion of each of the pads 122 andfurther covers the first surface 104 a of the semiconductor element 104.The insulation layer 124 has at least one opening 1241. Each opening1241 exposes at least a portion of a pad 122. and a UBM 126 is disposedin the opening 1241 and contacts the pad 122. The insulation layer 124may be, for example, a solder mask (the material of which is, forexample, PI) or a passivation layer (the material of which is a metaloxide). In an embodiment, the UBMs 126 may be formed from a metal, metalalloy, multi-metal or multi-alloy stack, such as a multi-alloy stackincluding, for example, a combination of copper, nickel, vanadium,chromium, and gold. The pillars 106 are disposed on respective UBMs 126and are physically bonded to and electrically connected to respectivebonding pads 108. The pillars 106 may comprise copper or another metal,or a metal alloy.

The underfill 110 is disposed between the semiconductor element 104 andthe substrate 102 to protect the pillars 106 from oxidation, moisture,and other environment conditions to meet the packaging applicationrequirements. It should be noted that the underfill 110 may not benecessary.

As described above, the pillars 106 are bonded to the bonding pads 108directly. That is, the solder material of the known process for bondingmay not be used, or may be reduced. Therefore, a pitch between thepillars 106 can be effectively reduced. In addition, the cavities 120are recessed from the top surface 102 a of the substrate 102, and thebonding pads 108 are disposed on the sidewalls of the cavities 120, suchthat the bonding pads 108 may also be recessed from the top surface 102a of the substrate 102. It is noted that since a portion of each pillar106 is accommodated within the substrate 102, (i.e., within the cavity120) and bonded to a bonding pad 108, such bonding structure can providea better lock-and-key effect.

FIG. 1A illustrates an enlarged view of an area A of a bonding structurein the semiconductor package 100 illustrated in FIG. 1. The bondingstructure connects the substrate 102 and the semiconductor element 104.In the portion of the bonding structure illustrated in FIG. 1A, thesubstrate 102 has the top surface 102 a, a cavity 120 and a bonding pad108. The cavity 120 has a cavity sidewall 120 a and a cavity bottom 120b. The cavity sidewall 120 a may be linear or curved, and isnon-perpendicular to the cavity bottom 120 b. The cavity sidewall 120 ais tapered at an angle θ1 relative to the cavity bottom 120 b, whereinthe angle θ1 may be about 90° to about 105°, about 90° to about 120°,about 90° to about 135°, about 90° to about 150°, about 90° to about165°, or about 90° to about 180° so that the cavity sidewall 120 a isinclined with respect to the cavity bottom 120 b. As shown in FIG. 1A, across section outline of the cavity 120 is a trapezoid shape. Such shapemay be formed by applying a dry etching process to the substrate 102. Inan embodiment, the dry etching process is carried out by using areactive plasma.

The bonding pad 108 is disposed on at least a portion of the cavitysidewall 120 a and at least a portion of the cavity bottom 120 b. Thebonding pad 108 conforms to the cavity sidewall 120 a and the cavitybottom 120 b, and has a pad bottom surface 108 b corresponding to thecavity bottom 120 b, and a sloped surface 108 a corresponding to thecavity sidewall 120 a. The sloped surface 108 a of the bonding pad 108has a slope (referred to in this disclosure as L1). The sloped surface108 a is tapered at an angle θ1 relative to the pad bottom surface 108b, wherein the angle θ1 may be about 90° to about 105°, about 90° toabout 120°, about 90° to about 135°, about 90° to about 150°, about 90°to about 165°, or about 90° to about 180° so that the sloped surface 108a is inclined with respect to the pad bottom surface 108 b. It is notedthat the sloped surface 108 a is also inclined with respect to the topsurface 102 a of the substrate 102. In addition, a portion of thebonding pad 108 that is not bonded with the pillar 106 is covered by apad metal oxide liner 136.

The bonding pad 108 defines an opening 130 (a space enclosed by thesloped surface 108 a of the bonding pad 108) which has a width from oneside of the opening 130 to the opposite side of the opening 130: amaximum width and a minimum width of the opening 130 are identified inFIG. 1 by W1 and W2, respectively, and the maximum width W1 is greaterthan the minimum width W2. As shown in FIG. 1A, a cross section outlineof the cavity 120 is in a trapezoid shape, and the bonding pad 108conforms to the shape of the cavity 120 along the cavity sidewall 120 aand the cavity bottom 120 b. Thus, in the embodiment illustrated in FIG.1A, the bonding pad 108 covers the cavity sidewall 120 a and the cavitybottom 120 b. Alternatively, in some embodiments, the bonding pad 108may be disposed on a portion of the cavity sidewall 120 a without beingdisposed on a portion of the cavity bottom 120 b; in other embodiments,the bonding pad 108 may cover the cavity sidewall 120 a without beingdisposed on a portion of the cavity bottom 120 b; and in yet otherembodiments, the bonding pad 108 may be disposed on a portion of thecavity sidewall 120 a and cover the cavity bottom 120 b.

As also illustrated in FIG. 1A, the pillar 106 is disposed on the UBM126 of the semiconductor element 104. The metal pillar 106 is bonded toa portion of the sloped surface 108 a of the bonding pad 108 of thesubstrate 102, to electrically connect the semiconductor element 104 tothe substrate 102. The pillar 106 has a sidewall 106 a and a pillarmetal oxide liner 132. The pillar metal oxide liner 132 is formed on aportion of the sidewall 106 a that is not bonded with the bonding pad108. The sidewall 106 a has a slope (referred to in this disclosure asL2). In the embodiment illustrated in FIG. 1A, the sidewall 106 a issubstantially perpendicular to the top surface 102 a of the substrate102, and the absolute value of the slope L1 of the sloped surface 108 ais less than the absolute value of the slope L2 of the sidewall 106 a.An average width W3 of the pillar 106 is designed to be greater than theminimum width W2 of the opening 130 and less than the maximum width W1of the opening 130. Therefore, during assembly, when the pillar 106 ismoved toward the bonding pad 108, the pillar 106 will contact a portionof the sloped surface 108 a of the bonding pad 108, and a gap 128 isformed between the sidewall 106 a of the pillar 106 and the slopedsurface 108 a of the bonding pad 108. In an embodiment, the averagewidth W3 refers to an average diameter of a pillar 106. By defining theaverage width W3 of the pillar 106 to be greater than the minimum widthW2 and less than the maximum width W1 of the opening 130, the pillar 106can be disposed on the bonding pad 108 in a more efficient and concisemanner by contacting the sloped surface 108 a of the bonding pad 108first.

The sidewall 106 a is inclined at an angle θ2 relative to the slopedsurface 108 a of the bonding pad 108. The angle θ2 can be about 0° toabout 90°, about 0° to about 15°, about 15° to about 30°, about 30° toabout 45°, about 45° to about 60°, about 60° to about 75°, or about 75°to about 90° to form the gap 128. By defining the angle θ2, or definingthe absolute value of the slope L1 of the sloped surface 108 a to beless than the absolute value of the slope L2 of the sidewall 106 a, theeffects mentioned above (i.e., the pillar 106 can be disposed on thebonding pad 108 in a more efficient and concise manner by contacting thesloped surface 108 a of the bonding pad 108 first) can also be achieved.

The slope of the sloped surface 108 a allows the pillar 106 to slidealong the sloped surface 108 a during flip-chip bonding, so that even ifthe alignment accuracy between the substrate 102 and the semiconductorelement 104 is poor, the pillar 106 can still be disposed in the opening130 and properly contact the pad bottom surface 108 b of the bonding pad108, to provide for more reliable bonding. Therefore, the alignmenttolerance of the flip-chip bonding structure can be improved. In oneembodiment, the material of the bonding pad 108 is the same as that ofthe pillar 106 (e.g., both are copper), and the pillar 106 is bonded tothe bonding pad 108 by metal fusion bonding or a metal eutectic bondingsuch that there is no actual interface between the pillar 106 and thebonding pad 108 after bonding. Accordingly, the dotted line between thepillar 106 and the bonding pad 108 in FIG. 1A is provided by way ofillustration, and does not necessarily represent an actual interface.

FIG. 1B illustrates a bonding structure according to another embodimentof the present disclosure. The bonding structure of this embodiment issimilar to the bonding structure illustrated in FIG. 1A, except that thecross section view of the cavity 120 is in a V shape. That is, thecavity sidewalls 120 a intersect and form a peak 120 c (pointingdownward in the orientation of FIG. 1B). Therefore, the cavity 120 doesnot have a cavity bottom as was shown in FIG. 1A. Such a V shape may beformed by applying a wet etching process to the substrate 102. In anembodiment, the wet etching process uses potassium hydroxide as anetchant. In the embodiment of FIG. 1B, the bonding pad 108 is disposedon at least a portion of the cavity sidewalls 120 a. The bonding pad 108conforms to the cavity sidewalls 120 a and has the sloped surfaces 108 acorresponding to the cavity sidewalls 120 a. Such sloped surfaces 108 aintersect at the peak of the V-shape of the cavity 120. Therefore, thecross section view of the bonding pad 108 that conforms to the V-shapeof the cavity 120 may also have a V-shape. As shown in FIG. 1B, theV-shaped bonding pad 108 has a peak substantially aligned with the peak120 c of the cavity 120. As a result, an interspace 134 is formedbetween the top surface 106 b (i.e., the top end) of the pillar 106 anda portion of the V-shaped bonding pad 108 around its peak. In oneembodiment, the bonding pad 108 may be disposed on a portion of thecavity sidewalls 120 a, without intersecting to form a peak.

The bonding pad 108 also defines an opening 130 which has a width fromone side of the opening 130 to the opposite side of the opening 130,where a maximum width W1 of the opening 130 is greater than an averagewidth W3 of the pillar 106.

FIG. 2 illustrates a cross-sectional view of a semiconductor package 200according to another embodiment of the present disclosure. Thesemiconductor package 200 is similar to the semiconductor package 100illustrated in FIG. 1 except that bonding pads 208 are disposed on thetop surface 102 a of the substrate 102 rather than being recessed fromthe top surface 102 a of the substrate 102 (as shown in FIG. 1 for thebonding pads 108). Further, an insulation layer 236 is disposed betweenthe bonding pads 208 and between the pillars 106, and contacts theinsulation layer 124. The substrate 102 may be, for example, asemiconductor substrate, a printed circuit board (PCB), a ceramicsubstrate, or a glass substrate.

FIG. 2A illustrates an enlarged view of an area B of the bondingstructure in the semiconductor package 200 illustrated in FIG. 2. Thebonding structure connects the substrate 102 and the semiconductorelement 104. In the portion of the bonding structure illustrated in FIG.1B, the substrate 102 has the top surface 102 a and at least one bondingpad 208. In this embodiment, the bonding pad 208 is disposed on the topsurface 102 a of the substrate 102. The bonding pad 208 is a taperedring structure, which has a pad outer side surface 208 a, a slopedsurface 208 b, and a pad top surface 208 c extending from the pad outerside surface 208 a to the sloped surface 208 b. The sloped surface 208 bof the bonding pad 208 has a slope referred to in this disclosure as L3.The pad outer side surface 208 a of the bonding pad 208 is substantiallyperpendicular to the top surface 102 a of the substrate 102, and thesloped surface 208 b is tapered at an angle θ1 relative to the topsurface 102 a of the substrate 102 and tapered at an angle θ2 relativeto the sidewall 106 a of the pillar 106. The angle θ1 may be about 90°to about 105°, about 90° to about 120°, about 90° to about 135°, about90° to about 150°, about 90° to about 165°, or about 90° to about 180°so that the sloped surface 208 b is inclined with respect to the topsurface 102 a of the substrate 102. The angle θ2 may be about 0° toabout 90°, about 0° to about 15°, about 15° to about 30° , about 30° toabout 45°, about 45° to about 60°, about 60° to about 75°, or about 75°to about 90°, to form the gap 128.

The bonding pad 208 defines an opening 230 (a space enclosed by thesloped surface 208 b of the bonding pad 208), and exposes a portion ofthe top surface 102 a of the substrate 102. The opening 230 has a widthfrom one side of the opening 230 to the opposite side of the opening230, where a maximum width of the opening 230 is shown as W1, a minimumwidth of the opening 230 is shown as W2, and the maximum width W1 isgreater than the minimum width W2. In addition, an exposed portion ofthe top surface 102 a of the substrate 102 has a width W2.

As also illustrated in FIG. 2A, the pillar 106 is disposed on the UBM126 of the semiconductor element 104. The pillar 106 is bonded to aportion of the sloped surface 208 b of the bonding pad 208 toelectrically connect the semiconductor element 104 to the substrate 102.The pillar 106 has a sidewall 106 a with a slope referred to in thisdisclosure as L4. In the embodiment illustrated in FIG. 2A, the sidewall106 a is substantially perpendicular to the top surface 102 a of thesubstrate 102, and the absolute value of the slope L3 is less than theabsolute value of the slope L4. An average width W3 of the pillar 106 isdesigned to be greater than the minimum width W2 of the opening 230, andless than the maximum width W1 of the opening 230. Therefore, duringassembly, when the pillar 106 is moved toward the bonding pad 208, thepillar 106 will contact a portion of the sloped surface 208 b of thebonding pad 108, and a gap 128 is formed between a sidewall 106 a of thepillar 106 and the sloped surface 208 b of the bonding pad 208. In anembodiment, the average width W3 refers to the average diameter of apillar 106. By defining the average width W3 of the pillar 106 to begreater than the minimum width W2 of the opening 230 and less than themaximum width W1 of the opening 230, or by defining the sloped surface208 b being inclined with respect to the sidewall 106 a of the pillar106 at the angle θ2, or by defining the absolute value of the slope L3to be less than the absolute value of the slope L4, the pillar 106 canbe disposed on the bonding pad 208 in a more efficient and concisemanner.

As stated above, the slope of the sloped surface 208 b allows the pillar106 to slide along the sloped surface 208 b during flip-chip bonding, toimprove the bonding contact and the alignment tolerance of the flip-chipbonding structure.

In addition, the first insulation layer 236 is disposed between thebonding pads 208, and contacts the insulation layer 124 to provideprotection from oxidation, moisture, and other environment conditions tomeet the packaging application requirements. As a result, an underfillto fill the space between the substrate 102 and the semiconductorelement 104 will not be necessary.

FIG. 2B illustrates a bonding structure according to another embodimentof the present disclosure. The bonding structure of this embodiment issimilar to the bonding structure illustrated in FIG. 2A, except that thepad outer side surface 208 a of the bonding pad 208 is tapered at anangle θ3 relative to the top surface 102 a of the substrate 102. Theangle θ3 may be about 90° to about 105°, about 90° to about 120°, about90° to about 135°, about 90° to about 150°, about 90° to about 165°, orabout 90° to about 180° so that the pad outer side surface 208 a of thepad 208 is inclined with respect to the top surface 102 a of thesubstrate 102.

FIG. 3 illustrates a cross-sectional view of a semiconductor package 300according to another embodiment of the present disclosure. Thesemiconductor package 300 comprises a first substrate 302, a secondsubstrate 303, a semiconductor device 305, a molding compound 311 and aplurality of connecting elements 312. The first substrate 302 has a topsurface 302 a, a bottom surface 302 b, a plurality of bonding pads 208,and a plurality of bottom pads 313. The bonding pads 208 are disposed onthe top surface 302 a, and the bottom pads 313 are disposed adjacent tothe bottom surface 302 b. The bonding pads 208 are electricallyconnected to the bottom pads 313. The connecting elements 312 aredisposed on the bottom pads 313 for external connection.

The semiconductor device 305 is mounted and electrically connected tothe top surface 302 a of the first substrate 302. In an embodiment, thesemiconductor device 305 may be electrically connected to the topsurface 302 a of the first substrate 302 through a plurality ofinterconnectors 307, such as copper pillars or respectivesolder/stud/bumps, positioned on respective pads of a bottom surface 305b of the semiconductor device 305 and on respective pads of the topsurface 302 a of the first substrate 302. The semiconductor device 305may be, for example, a die or a semiconductor chip.

The second substrate 303 may be an interposer, and has a top surface 303a, a bottom surface 303 b, a plurality of top pads 309, a plurality ofbottom pads 304 and a plurality of pillars 106. The top pads 309 aredisposed adjacent to the top surface 303 a, and the bottom pads 304 aredisposed adjacent to the bottom surface 303 b. The top pads 309 areelectrically connected to the bottom pads 304. The pillars 106 aredisposed on the bottom pads 304 of the second substrate 303 and bondedto the bonding pads 208 of the first substrate 302. It is noted that thebonding structure formed by the pillars 106 and the bonding pad 208 inthis embodiment is similar to the bonding structure formed by thepillars 106 and the bonding pad 208 of FIG. 2 and FIG. 2A. The moldingcompound 311 is disposed between the bottom surface 303 b of the secondsubstrate 303 and the top surface 302 a of the first substrate 302, andcoves the semiconductor device 305 and the pillars 106 to provideprotection from oxidation, moisture, and other environment conditions.

FIG. 4A, FIG. 4B, FIG. 4C, FIG. 4D, FIG. 4E, FIG. 4F, FIG. 4G, FIG. 4H,FIG. 4I, FIG. 4J and FIG. 4K illustrate a method for manufacturing thesemiconductor package 100 according to an embodiment of the presentdisclosure. For example, this method can be used to manufacture thebonding structure of FIG. 1A.

Referring to FIG. 4A, the substrate 102 is provided. The substrate 102of FIG. 4A is the same as the substrate 102 of FIG. 1 and FIG. 1A, andhas the top surface 102 a, the bottom surface 102 b, the side surface102 c, the lower circuit layer 114, the lower insulation layer 116, theconductive vias 118, the bonding pads 108 and the cavities 120. Thelower circuit layer 114 is disposed adjacent to the bottom surface 102 bof the substrate 102. The lower insulation layer 116 substantiallycovers the lower circuit layer 114 and the bottom surface 102 b of thesubstrate 102, and has a plurality of openings 1161 to expose at least aportion of the lower circuit layer 114. The bonding pads 108 aredisposed adjacent to the top surface 102 a of the substrate 102. In thisembodiment, each bonding pad 108 is formed in the cavity 120 of thesubstrate 102 and has a sloped surface 108 a with a slope L1 relative tothe top surface 102 a of the substrate 102, and the bonding pad 108defines an opening 130 (a space enclosed by the sloped surface 108 a ofthe bonding pad 108). The opening 130 has a width from one side to theopposite side of the opening 130, where the maximum width W1 of theopening 130 is greater than the minimum width W2 of the opening 130.

Referring to FIG. 4B, the semiconductor element 104 is provided. Thesemiconductor element 104 of FIG. 4B is the same as the semiconductorelement 104 of FIG. 1 and FIG. 1A, and has the first surface 104 a, thesecond surface 104 b, the side surface 104 c, the pads 122, theinsulation layer 124, the UBMs 126, and the pillars 106. The pads 122are disposed on the first surface 104 a of the semiconductor element104. The insulation layer 124 substantially covers the pads 122 and thetop surface 104 a of the semiconductor element 104, and has at least oneopening 1241 to expose at least a portion of a pad 122, and a UBM 126 isdisposed in the opening 1241 of the insulation layer 124 and contactsthe pad 122. A pillar 106 is disposed on the UBM 126.

Each pillar 106 has a sidewall 106 a with a slope L2, where the absolutevalue of the slope L1 of the sloped surface 108 a of the bonding pad 108is designed to be less than the absolute value of the slope L2 of thesidewall 106 a. The average width W3 of the pillar 106 is designed to begreater than the minimum width W2 of the opening 130 and less than themaximum width W1 of the opening 130. The pillar 106 further has a topsurface 106 b and an edge portion 106 c, and the edge portion 106 c isat the intersection of the sidewall 106 a of the pillar 106 and the topsurface 106 b of the pillar 106.

Referring to FIG. 4C, the pillar 106 of the semiconductor element 104 isbonded to a portion of the sloped surface 108 a of the bonding pad 108.For example, the bond between the pillar 106 and the bonding pad 108 maybe formed by thermo-compression bonding. During thermo-compressionbonding, an operation pressure may be from about 0.1 megaPascals (MPa)to about 10 MPa; the operation temperature may be from about 25° C. toabout 300° C., preferably from about 25° C. to about 180° C., and morepreferably from about 60° C. to about 160° C.; and the operation periodcan be from about 1 minute to about 160 minutes.

The pillar 106 is moved towards the sloped surface 108 a of the bondingpad 108 so as to form a line contact or a point contact between the edgeportion 106 c of the pillar 106 and the sloped surface 108 a of thebonding pad 108. By designing W2<W3<W1, a large effective local pressurewill occur at the contacting interface under a given tool bondingpressure since the contacting interface resides at the periphery of thetop surface 106 b of the pillar 106, of which the contacting interfaceis a line or a point contact, and the contact surface area is small.Thus, the bonding structure can be completed at a low temperature (e.g.,lower than about 180° C.), and warpage does not easily occur. In anembodiment, the bonding is carried out at a temperature of from about60° C. to about 160° C. In another embodiment, large effective localpressure can be achieved by providing the slope L1 with an absolutevalue less than the value of the slope L2. In another embodiment, largeeffective local pressure can be achieved by designing the angle θ2 (FIG.1A) to be about 0° to about 90°.

Referring to FIG. 4D, an enlarged view of an area C of a bondingstructure in FIG. 4C is illustrated. The edge portion 106 c of thepillar 106 is in touch with the sloped surface 108 a of the bonding pad108 by the pillar metal oxide liner 132 over the surface of the pillar106 and the pad metal oxide liner 136 over the surface of the bondingpad 108. Meanwhile, a space 138 is formed between the top surface 106 bof the pillar and the pad bottom surface 108 b of the bonding pad 108,and a gap 128 is formed between a sidewall 106 a of the pillar 106 andthe sloped surface 108 a of the bonding pad 108. The metal oxide liners132, 136 are typically formed over the surface of the pillar 106 and thebonding pad 108 if the pillar 106 and the bonding pad 108 are made of ametal or an alloy thereof and exposed to the atmosphere. The metal oxideliners 132, 136 could be a hindrance when the bonding between the pillar106 and the bonding pad 108 is performed. Accordingly, in someembodiments, a protection layer (including, for example, one of, or acombination of, gold, indium, tin, silver, palladium, osmium, iridium,ruthenium, titanium, magnesium, aluminum, cobalt, nickel, zinc) can becoated on the metal oxide liner 132 over the top surface 106 b of pillar106 or the metal oxide liner 136 over the bonding pad 108 to prevent themetal oxide liners 132, 136 from continuing formation. The thickness ofthe protection layer can be less than about 5 um.

FIG. 4E illustrates an enlarged view of an area D of the embodimentillustrated in FIG. 4D at initial contact between the metal pillar 106and the bonding pad 108 during thermo compression. As shown in FIG. 4E,the pillar 106 first contacts the bonding pad 108 by the edge portion106 c of the pillar 106, where the contacting interface is small. Thepillar metal oxide liner 132 of the pillar 106 and the pad metal oxideliner 136 of the sloped surface 108 a of the bonding pad 108 may formline contact or point contact. Therefore, a large effective localpressure will be produced at the contacting interface under a given toolbonding pressure because of the small contacting interface area. Inaddition, because the metal oxide liners 132, 136 at the smallcontacting interface are relatively thin, they will be penetrated andfractured more easily under a large effective local pressure.

Referring to FIG. 4F, as the pillar 106 is pressed against the bondingpad 108 further during the thermo-compression process, the edge portion106 c of the pillar 106 penetrates the pillar metal oxide liner 132, andthe pad metal oxide liner 136 is also penetrated around the area incontact with the sloped surface 108 a of the bonding pad 108. Under thiscircumstance, a metal fusion diffusion bonding between the edge portion106 c of the pillar 106 and the sloped surface 108 a of the bonding pad108 will occur because of the direct contact between the pillar 106 andthe bonding pad 108. Thus, a high temperature will not be necessary. Inaddition, the space 138 is compressed.

In another embodiment, if the protection layer is coated on the metaloxide liner 132 over the top surface 106 b of the pillar 106 and on themetal oxide liner 136 over the bonding pad 108, the edge portion 106 cof the pillar 106 will penetrate the protection layer on the metal oxideliner 132, and the protection layer on the metal oxide liner 136 willalso be penetrated around the area in contact with the sloped surface108 a of the bonding pad 108 when the pillar 106 is pressed against thebonding pad 108 further during the thermo-compression process. Underthis circumstance, since the protection layer may contain a species ofmetal different from that of the pillar 106 and the bonding pad 108(such as, for example, gold, indium, tin, silver, palladium, osmium,iridium, ruthenium, titanium, magnesium, aluminum, cobalt, nickel, zinc,or an alloy thereof), a metal eutectic bonding between the edge portion106 c of the pillar 106 and the sloped surface 108 a of the bonding pad108 will occur, which also can reduce the processing temperature. Inanother embodiment, the metal fusion diffusion bonding and the metaleutectic bonding occur substantially simultaneously.

Referring to FIG. 4G, as the pillar 106 is further pressed against thesloped surface 108 a of the bonding pad 108 during thethermo-compression process, the edge portion 106 c of the pillar 106penetrates the sloped surface 108 a of the bonding pad 108 and the metalions of the pillar 106 starts to diffuse into the bonding pad 108 andspread out. Thus, a metal fusion diffusion bonding occurs between thepillar 106 and the bonding pad 108. The space 138 is further compressed.In an embodiment, both the pillar 106 and the bonding pad 108 are madeof copper, and thus the metal ions are copper ions. In otherembodiments, as described above, if a protection layer is formed on thepillar 106, a metal fusion diffusion bonding and a metal eutecticbonding will occur substantially simultaneously.

Referring to FIG. 4H, as the pillar 106 is further pressed against thesloped surface 108 a of the bonding pad 108 during thethermo-compression process, more and more metal ions of the pillar 106diffuse into the bonding pad 108. In addition, increasingly more pillarmetal oxide liners 132 and pad metal oxide liner 136 are fractured.Meanwhile, the contact between the pillar 106 and the bonding pad 108becomes surface contact. In addition, the space 138 is furthercompressed and there is only limited space left between the pillar metaloxide liner 132 and the pad metal oxide liner 136.

Referring to FIG. 4I, as the pillar 106 continues to be pressed towardthe bonding pad 108 during the thermo-compression process, the pillarmetal oxide liner 132 of the pillar 106 and the pad metal oxide liner136 of the bonding pad 108 are fractured because of the continuingdiffusion of the metal ions, and the top surface 106 b of the pillar 106contacts the pad bottom surface 108 b of the bonding pad 108. Then, themetal oxide liners 132, 136 are crushed due to the push of the diffusionof the metal ions. It is noted that the interface 140 between the pillar106 and the bonding pad 108 is blurring and may not have a clearboundary at this stage.

Referring to FIG. 4J, as the thermo-compression process continues, moremetal ions inter-diffuse between the pillar 106 and the bonding pad 108and spread out. As a result, the interface 140 disappears, and oxygenions 142 in the original metal oxide liners 132, 136 are driven todiffuse and spread out. Therefore, the oxygen ions 142 are distributedin the diffusion layer between the pillar 106 and the bonding pad 108rather than being concentrated at the interface 140. Thus, the metaloxide liners 132, 136 are substantially reduced or eliminated betweenthe pillar 106 and the bonding pad 108, and the bonding of the pillar106 and the bonding pad 108 is complete.

Referring to FIG. 4K, a semiconductor package including the bondingstructure of FIG. 4J is illustrated after the bonding.

An underfill material may then be filled into the space between thesubstrate 102 and the semiconductor element 104 to form an underfill 110(FIG. 1) therein. The underfill 110 may be disposed between the pillars106 and may cover at least a portion of the top surface 102 a of thesubstrate 102 and at least a portion of the insulation layer 124. Then,the connecting elements 112 (FIG. 1) may be attached to the exposedlower circuit layer 114 in the opening 1161 of the lower protectionlayer 116 so as to obtain the semiconductor package 100 as illustratedin FIG. 1.

FIG. 5A and FIG. 5B illustrate a method for manufacturing asemiconductor package according to another embodiment of the presentdisclosure. For example, this method can be used to manufacture thesemiconductor package 200 described in connection with FIG. 2.

Referring to FIG. 5A, a substrate 102 and a semiconductor element 104are provided. The semiconductor element 104 of this embodiment is thesame as the semiconductor element 104 illustrated in FIG. 4B. Thesubstrate 102 of this embodiment is similar to the substrate 102illustrated in FIG. 4B, and the difference is described as follows. Inthis embodiment, the bonding pad 208 is disposed on the top surface 102a of the substrate 102 rather than being recessed from the top surface102 a of the substrate 102. The bonding pad 208 is a tapered ringstructure, which has a sloped surface 208 a. The substrate 102 includesan insulation layer 236 disposed on the top surface 102 a of thesubstrate 102 and between the bonding pads 208.

Referring to FIG. 5B, the semiconductor element 104 is moved to thesubstrate 102 so that the edge portion 106 c of the pillar 106 contactsthe sloped surface 108 a of the bonding pad 108. Then, the pillar 106 ofthe semiconductor element 104 is bonded to a portion of the slopedsurface 108 a of the bonding pad 108 using thermo-compression, such asusing the thermo-compression described above. In addition, theinsulation layer 236 will contact and combine with the insulation layer124 to provide protection from oxidation, moisture, and otherenvironment conditions. In this embodiment, an underfill will not benecessary and a cost in this regard can be reduced. After thesemiconductor element 104 and the substrate 102 are bonded together, theconnecting elements 112 may be attached to the exposed lower circuitlayer 114 of the semiconductor element 104 so as to obtain thesemiconductor package 200 as illustrated in FIG. 2.

As used herein and not otherwise defined, the terms “substantially” and“about” are used to describe and account for small variations. When usedin conjunction with an event or circumstance, the terms can refer toinstances in which the event or circumstance occurs precisely as well asinstances in which the event or circumstance occurs to a closeapproximation. For example, the terms can refer to less than or equal to±10%, such as less than or equal to ±5%, less than or equal to ±4%, lessthan or equal to ±3%, less than or equal to ±2%, less than or equal to±1%, less than or equal to ±0.5%, less than or equal to ±0.1%, or lessthan or equal to ±0.05%. Additionally, “substantially perpendicular” asused in this disclosure is accounts for small angular variations from90°, such as less than or equal to ±1°, less than or equal to ±2°, lessthan or equal to ±3°, less than or equal to ±4°, or less than or equalto ±5°. Further, “substantially simultaneously” as used in thisdisclosure accounts for small variations in time, such as less than orequal to ±1 microsecond, less than or equal to ±1 millisecond, or lessthan or equal to ±1 second.

Additionally, amounts, ratios, and other numerical values are sometimespresented herein in a range format. It is to be understood that suchrange format is used for convenience and brevity and should beunderstood flexibly to include numerical values explicitly specified aslimits of a range, but also to include all individual numerical valuesor sub-ranges encompassed within that range as if each numerical valueand sub-range is explicitly specified.

While the present disclosure has been described and illustrated withreference to specific embodiments thereof, these descriptions andillustrations do not limit the present disclosure. It should beunderstood by those skilled in the art that various changes may be madeand equivalents may be substituted without departing from the truespirit and scope of the present disclosure as defined by the appendedclaims. The illustrations may not be necessarily be drawn to scale.There may be distinctions between the artistic renditions in the presentdisclosure and the actual apparatus due to manufacturing processes andtolerances. There may be other embodiments of the present disclosurewhich are not specifically illustrated. The specification and drawingsare to be regarded as illustrative rather than restrictive.Modifications may be made to adapt a particular situation, material,composition of matter, method, or process to the objective, spirit andscope of the present disclosure. All such modifications are intended tobe within the scope of the claims appended hereto. While the methodsdisclosed herein have been described with reference to particularoperations performed in a particular order, it will be understood thatthese operations may be combined, sub-divided, or re-ordered to form anequivalent method without departing from the teachings of the presentdisclosure. Accordingly, unless specifically indicated herein, the orderand grouping of the operations are not limitations of the presentdisclosure.

What is claimed is:
 1. A bonding structure, comprising: a substrate,having a top surface and comprising at least one bonding pad, whereinthe bonding pad is disposed adjacent to the top surface of the substrateand has a sloped surface; and a semiconductor element, comprising atleast one pillar; wherein each pillar is bonded to a portion of thesloped surface of a corresponding one of the at least one bonding pad,and a gap is formed between a sidewall of the pillar and the slopedsurface of the corresponding bonding pad; wherein the substrate furthercomprises a first insulation layer disposed on the top surface thereofand between the bonding pads, and the semiconductor element furthercomprises a second insulation layer between the pillars, wherein thefirst insulation layer contacts the second insulation layer.
 2. Thebonding structure of claim 1, wherein the substrate defines at least onecavity, and each bonding pad is disposed on a sidewall of acorresponding one of the at least one cavity.
 3. The bonding structureof claim 2, wherein a cross section of at least one cavity is in a Vshape or a trapezoid shape.
 4. The bonding structure of claim 2, whereinan interspace is formed between an end of each pillar and a portion ofthe corresponding bonding pad.
 5. The bonding structure of claim 1,wherein the at least one bonding pad is disposed on the top surface ofthe substrate and at least one bonding pad is a tapered ring structure.6. The bonding structure of claim 5, wherein at least one bonding padexposes a portion of the top surface of the substrate.
 7. The bondingstructure of claim 1, wherein there is an inclination angle between thesidewall of at least one pillar and the sloped surface of thecorresponding bonding pad.
 8. The bonding structure of claim 1, whereina space defined by the sloped surface of at least one bonding pad has amaximum width and a minimum width, and a width of the correspondingpillar is greater than the minimum width of the space and less than themaximum width of the space.
 9. A bonding structure, comprising: asubstrate, having a top surface and comprising at least one bonding pad,wherein each bonding pad is disposed adjacent to the top surface of thesubstrate and has a sloped surface with a first slope; and asemiconductor element, comprising at least one pillar, wherein eachpillar is bonded to a portion of the sloped surface of a correspondingone of the at least one bonding pad and has a sidewall with a secondslope, and wherein the absolute value of the first slope is less thanthe absolute value of the second slope.
 10. The bonding structure ofclaim 9, wherein the substrate defines at least one cavity, and at leastone bonding pad is disposed on a sidewall of a corresponding one of theat least one cavity.
 11. The bonding structure of claim 10, wherein across section of at least one cavity is in a V shape or a trapezoidshape.
 12. The bonding structure of claim 10, wherein an interspace isformed between an end of at least one pillar and a portion of thecorresponding bonding pad.
 13. The bonding structure of claim 10,wherein a portion of each pillar is accommodated within thecorresponding one of the at least one cavity.
 14. The bonding structureof claim 9, wherein the bonding pads are disposed on the top surface ofthe substrate and at least one bonding pad is a tapered ring structure.15. The bonding structure of claim 14, wherein at least one bonding padexposes a portion of the top surface of the substrate.
 16. The bondingstructure of claim 9, wherein the substrate further comprises a firstinsulation layer disposed on the top surface thereof and between thebonding pads, and the semiconductor element further comprises a secondinsulation layer between the pillars, wherein the first insulation layercontacts the second insulation layer.
 17. The bonding structure of claim9, wherein there is an inclination angle between the sidewall of atleast one pillar and the sloped surface of a corresponding one of the atleast one bonding pad.
 18. The bonding structure of claim 17, whereinthe inclination angle is 0° to about 90°.
 19. The bonding structure ofclaim 9, wherein a space defined by the sloped surface of at least onebonding pad has a maximum width and a minimum width, and a width of acorresponding one of the at least one pillar is greater than the minimumwidth of the space and less than the maximum width of the space.